Howdy!
You can visit http://cegroup.ece.tamu.edu/~kirang/ or
http:/dropzone.tamu.edu/~kirang/
to visit my Texas A&M web page. This website is essentially the same as above web pages.
**************************************************************************************************
This website is mainly for the public distribution of of my PhD research work on Efficient hardware architectures for LDPC Decoder at Texas A&M University.
My IEEE publications can be downloaded from here:
http://ieeexplore.ieee.org/search/freesearchresult.jsp?history=yes&queryText=%28gunnam%29
Here are the various public presentations on my PhD research:
October 2006:[Posted online October 2006]
My PhD Defense Presentation, October 11 2006
Same presentation was given in October 3rd weeks and October 4th weeks at Asilomar 2006 conference presentation, Marvell Semiconductor (Santa Clara) and Texas Instruments (Dallas).
Parts of the above presentation were given in the following international conferences:
January 2007: VLSI Conference
Febraury 2007: ISWPC Conference
May 2007: ISCAS Conference
June 2007: ICC Conference
Slighly condensed version of the my PhD defense presentation was given at a IEEE Solid-State Circuits chapter meeting in bay area
Febraury 2008: IEEE SSC SCV Chapter Meeting
Research Highlights
My PhD research introduced the following concepts to LDPC decoder implementation:
1. Block serial scheduling,
2. Value-reuse,
3. Scheduling of layered processing(or layer re-ordering) (to remove the pipeline stalls and memory conflicts),
4. Out-of-order block processing, (to remove the pipeline stalls and memory conflicts),
5. Master-slave routers and multi-circulant size shifter, (to support cyclic shifts on different circulant sizes)
6. Dynamic state,
7. Speculative Computation, (to schedule several speculative parallel computations to avoid pipeline penalty-mainly for the control path)
8. Run-time Application Compiler [support for different LDPC codes with in a class of codes.
Class:802.11n,802.16e,Array, etc. Off-line re-configurable for several regular and irregular LDPC codes]
9. Statistical Buffering of input and output memories to serve maximum iterations while having the decoder
parallelization is based on the average number of iterations required. All these concepts are termed as On-the-fly computation as the core of these concepts are based on minimizing memory and re-computations by employing just in-time scheduling.
-Elected as IEEE Senior Member in April 2007 for significant contributions in integrated circuit design for signal processing and communication systems(visnav sensor signal processing, LDPC VLSI architectures).
My linked in profile is
http://www.linkedin.com/pub/kiran-gunnam/2/551/884
Contact Info
Please e-mail to [kgunnam(AT)ieee(DOT)org] if you need any clarifications on my work. I appreciate appropriate and correct citation of my work.